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How to design a multi-channel data acquisition system FIFO?

 
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kkone
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Joined: 01 Apr 2021
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Location: Hong Kong

PostPosted: Thu May 13, 2021 7:58 am    Post subject: How to design a multi-channel data acquisition system FIFO? Reply with quote

First, the overall design of the multi-channel data acquisition system is introduced, and the FIFO chip IDT7202 is introduced. The design method of FIFO and CPLD, AD interface is then analyzed separately. The analog-to-bit digital conversion is completed by the 16-bit modulus of the chip AD976, and the various timing controls of the cache and transmission of the data are completed by Atera's programmable FPGA devices logic EPM7256A. The FIFO device is used as the data buffer between the high speed A / D and the DSP processor, effectively improves the work efficiency of the processor.
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